ProcSys Campus Selection Process for 2018-2019 Batch Engg. Students
ProcSys invites prospective engineers to join us in the following roles:
? Design Engineer: Hardware/FPGA
? Design Engineer: Embedded Software
? Design Engineer: Application Software
Candidates with 70% aggregate marks with a history of maximum 2 back papers are eligible to apply. The can
? Electronics & Communication
? Electronics & Instrumentation
? Electronics & Telecommunication
? Computer Science
? Information Science / Technology
The selection process will be conducted in 2 phases:
Phase 1: Written Test containing multiple choice questions and descriptive questions. The test duration will be 2.5 hours. The questions will be separate and specific for each role. Please refer to the sections further for details on the topics to prepare for the test. Only candidates who clear Phase 1 will be eligible for Phase 2.
Phase 2: Face to Face Interview. This will be held on a later date. The details of the schedule and selected candidates will be informed to the respective placement coordinators.
didate should be pursuing one of the following engineering streams: